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? e95704e0z-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd +0.5 to v ss ?.5 v output voltage (for each channel) i out 0 to 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 5.0 0.25 v dv dd , dv ss 5.0 0.25 v reference input voltage v ref 0.5 to 2.0 v clock pulse width tpw 1 , tpw 0 5.6 (min.) ns operating temperature topr ?0 to +85 ? description the CXD2315Q is a 1-ch 10-bit 80msps d/a converter for monitor and video. this ic achieves high specifications for the industrial and information equipment due to the reduction of the glitch energy. features 10-bit resolution maximum conversion rate 80msps differential linearity error ?.5lsb low power consumption 150 mw (max., when 80msps 200 ? load, 2 vp-p is output) pin-compatible with cxd2306q single 5 v power supply built-in independent constant-voltage source ultra-low glitch stand-by function structure silicon gate cmos ic 10-bit 80msps 1ch d/a converter (ultra-low glitch version) 32 pin qfp (plastic) CXD2315Q
? CXD2315Q block diagram pin configuration 17 18 19 20 21 22 23 24 25 4lsb's current cells 6msb's current cells bias voltage generator band gap reference clock generator decoder decoder latches 2 3 4 5 6 7 9 10 11 13 14 27 28 30 31 32 1 15 (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 dv dd blk dv dd dv ss dv ss clk vb ce io av ss io vg av dd av dd current cells (for full scale) vref iref sref 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 27 15 17 25 avss nc dvss dv dd nc d0 (lsb) d1 d2 nc dvss vb dv dd nc ce blk clk d3 d4 d5 d6 d7 d8 d9 (msb) nc to to digital section analog section io io vg av dd av dd vref sref iref
3 CXD2315Q pin description and equivalent circuit 30 to 32 1 to 7 8, 12, 16, 26, 29 9 10 11 13, 28 14 15, 27 17 19 22 d0 to d9 nc clk blk ce dv dd vb dv ss iref vref vg i i o o i o pin no. symbol i/o equivalent circuit description dv dd 7 30 dv dd dv ss to 10 11 9 dv dd dv ss 14 dv dd dv dd dv ss avss 19 22 17 av dd av dd av dd av dd av ss av ss digital input. 30 pin d0 (lsb) to 7 pin d9 (msb) no connection. clock input. blanking input. this is synchronized with the clock input signal. no signal (0 v output) at high and output state at low. chip enable input. this is not synchronized with the clock input signal. no signal (0 v output) at high makes power consumption minimum. digital power supply. connect a capacitor of approximately 0.1 f. digital ground. reference current output. connect resistance r ir which is 16 times output resistance r out . reference voltage input. sets output full scale value. connect a capacitor of approximately 0.1 f.
4 CXD2315Q 18 20, 21 23 24 25 sref av dd io io av ss o o pin no. symbol i/o equivalent circuit description 18 av dd av ss av ss 23 24 av ss av ss independent constant-voltage source output pin using band gap reference. stable voltage independent of the fluctuation for supply voltage can be get by connecting to v ref . see application circuit 2 for details. analog v dd inverted current output. connect to gnd normally. current output. output can be retrieved by connecting resistance. the standard is 200 ? . analog ground.
5 CXD2315Q electrical characteristics (f clk =80 mhz, av dd =dv dd =5 v, r out =200 ? , r ir =3.3 k ? , v ref =2.0 v, ta=25 c) item resolution conversion speed integral non-linearity error differential non-linearity error precision guaranteed output voltage range output full-scale voltage output full-scale current output offset voltage glitch energy differential gain differential phase supply current analog input resistance input capacitance digital input voltage digital input current sref output voltage setup time hold time rise time propagation delay time ce enable time ? ce disable time ? symbol n f clk e l e d v oc v fs i fs v os ge dg dp i dd i stb r in c i v ih v il i ih i il v sr ts th tr t pd t e t d measurement conditions av dd =dv dd =4.75 to 5.25 v ta= 20 to +85 c endpoint when d0 to d9= 0000000000 input ce= l ce= h vref av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c ce= h l ce= l h min. 0 1.5 0.5 1.8 1.8 9.0 1 2.45 5 1.0 3.0 3.0 5 typ. 10 1.94 1.94 9.7 1.2 5 1 1 max. 80 1.5 0.5 2.0 2.0 10 1 30 1.0 1.0 30 1 9 0.85 5 1.45 2 2 unit bit msps lsb lsb v v ma mv pv s % deg ma m ? pf v a v ns ns ns ns ms ms electrical characteristics measurement circuit analog input resistance measurement circuit digital input current CXD2315Q +5.25v av dd , dv dd av ss , dv ss v a } ? when the external capacitor for the vgr,vgg and vgb pins are 0.1 f.
6 CXD2315Q maximum conversion rate measurement circuit 9 7 30 31 10 11 14 17 19 22 24 10bit counter with latch d0 (lsb) clk blk ce vb d9 (msb) io vg vref iref 0.1 2v 3.3k avss 5k av dd 200 oscilloscope 0.1 clk 80mhz (max) square wave dc characteristics measurement circuit 9 7 30 31 10 11 14 17 19 22 controller d0 (lsb) clk blk ce vb d9 (msb) io vg vref iref 0.1 2v 3.3k avss 5k av dd 200 dvm 0.1 24 clk 80mhz square wave propagation delay time measurement circuit 9 7 30 31 10 11 14 17 19 22 d0 (lsb) clk blk ce vb d9 (msb) io vg vref iref 0.1 2v 3.3k avss 5k av dd 200 oscilloscope 0.1 frequency demultiplier 24 clk 10mhz square wave 7 30 31 17 19 22 10bit counter with latch d0 (lsb) clk blk ce vb d9 (msb) io vg vref iref 0.1 2v 3.3k avss 5k av dd 200 oscilloscope 0.1 delay controller 10 11 14 9 delay controller 24 clk 1mhz square wave setup time hold time measurement circuit glitch energy }
7 CXD2315Q description of operation timing chart t pw1 t pw0 ts th ts th ts th t pd t pd t pd clk data d/a out 100% 50% 0% 1.5v msb lsb 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 2.0 v 1.0 v 0 v input code output voltage i/o correspondence table (when 2.00 v output full-scale voltage)
8 CXD2315Q application circuit 1 avss nc dvss dv dd nc d0 d1 d2 nc dvss vb dv dd nc ce blk clk 2 3 4 5 6 7 8 1 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 io io vg av dd av dd vref sref iref d3 d4 d5 d6 d7 d8 d9 nc c c c r1 c r3 r4 r2 clock input av dd av ss dv dd dv ss when 5.0v supply voltage (dv dd and av dd ) digital input from pins 30 to 32 and pins 1 to 7 pin 18 is left open when using normally r1=200 ? r2=3.3k ? (resistance 16 times r1) (r ir ) r3=3.0k ? r4=2.0k ? c=0.1f application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
9 CXD2315Q application circuit 2 avss nc dvss dv dd nc d0 d1 d2 nc dvss vb dv dd nc ce blk clk 2 3 4 5 6 7 8 1 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 io io vg av dd av dd vref sref iref d3 d4 d5 d6 d7 d8 d9 nc c c c r1 c r2 clock input av dd av ss dv dd dv ss when 5.0v supply voltage (dv dd and av dd ) digital input from pins 30 to 32 and pins 1 to 7 r1=200 ? r2=2.0k ? c =0.1f cr =4.7f cr application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXD2315Q notes on operation selecting the output resistance CXD2315Q is a current output type d/a converter. to create the output voltage, connect the resistor to the current output pin io. specifications: output full-scale voltage v fs = 1.8 to 2.0 [v] output full-scale current i fs = 10 or less [ma] calculate the output resistance from v fs = i fs r out . connect a resistance sixteen times the output resistance to the reference current pin iref. in some cases, as this value may not exist, a similar value can be used instead. note that the v fs will be the following. v fs = v ref 16 r out /r v ref is the voltage set at the vref pin, r out is the resistor to be connected to the current output pin io and r ir is the resistor to be connected to the iref. power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data settling time. set the best values according to the purpose of use. correlation between data and clock for the CXD2315Q to display the desired performance as a d/a converter, the data transmitted from outside and the clock must be synchronized properly. adjust the setup time (ts) and hold time (th) as specified in electrical characteristics . power supply and ground separate the analog and digital power supplies and grounds around the device to reduce noise effects. by- pass the power supply pin to each ground with a 0.1 f ceramics capacitor as near to the pin as possible for both the digital and analog signals. latch up analog and digital power supply must be able to share the same power supply of the board. this is to prevent latch up caused by potential difference between the two pins when the power is turned on. iref pin the iref pin is very sensitive to improve the ac characteristics. pay attention for capacitance component not to attach to this pin because its output may become unstable. vg pin it is recommended to use a 1 f capacitor to improve the ac characteristics though the typical capacitance value externally connected to the vg pin is 0.1 f. sref sref is an independent regulated voltage source. by connecting the sref pin and the vref pin, stable output amplitudes that do not depend on fluctuations in the power supply can be obtained. in this case, as described above, v fs = v sr 16r out /r ir , set the v fs according to r ir . v sr is the output voltage of the sref pin. do not use this pin as a reference power supply for other ics because this is dedicated for the vg pin of the CXD2315Q.
11 CXD2315Q ge (glitch energy) ge, described in the CXD2315Q, is a spike noise which appears synchronizing with the clock falling edge when the input data (for 1 to 1024 input) changes to 128, 256, 384, 512, 640, 768, 896, and 1024. fig. 1 shows the change state of ge for the staircase wave output, and fig. 2 shows the repetitive output waveform where the ge appears. these figures exhibit the difference of this ic from the conventional device. conventional device CXD2315Q clk 2.0 1.0 05121024 analog output [v] digital input [v] fig. 1. change of ge for staircase wave output fig. 2. repetitive output waveform where ge appears (for 200 ? , 2 vp-p output) the CXD2315Q reduces the ge much shown in fig.s 1 and 2. conventional device (ge typ.=200pv-s) CXD2315Q (ge typ.=10pv-s) io pin the io pin is the inverted current output pin described in the pin description. the sum of the currents output from the io pin and the io pin becomes the constant value for any input data. however, the performances such as the linearity error of the io pin output current is not guaranteed.
12 CXD2315Q +5v c av ss dv ss av ss dv ss av dd dv dd c dv dd digital ic CXD2315Q 20 21 28 15 27 25 13 latch up prevention the CXD2315Q is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd (pins 20 and 21) and dv dd (pins 13 and 28), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd dv dd digital ic c CXD2315Q 20 21 28 15 27 25 13 c +5v av ss dv ss av ss dv ss av dd dv dd dv dd digital ic c CXD2315Q 20 21 28 15 27 25 13 c +5v
13 CXD2315Q 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd dv dd digital ic c CXD2315Q 20 21 28 15 27 25 13 c +5v c av ss dv ss av ss dv ss av dd dv dd dv dd digital ic av dd CXD2315Q 20 21 28 15 27 25 13 c +5v +5v av ss dv ss av ss dv ss av dd dv dd CXD2315Q dv dd digital ic av dd 20 21 28 15 27 25 13 c
14 CXD2315Q 2.0 1.0 2.0 1.0 fig. 3. reference voltage vs.output full-scale voltage output full-scale voltage v fs [v] reference voltage v ref [v] 30 20 40 1 fig. 6. output frequency vs. supply current supply current i dd [ma] output frequency fo [mhz] 10 20 30 0 1.25 1.15 75 25 fig. 5. ambient temperature vs. sref output voltage sref output voltage v sr [v] ambient temperature ta [ c] 0 25 50 0 1.95 1.93 75 25 fig. 4. ambient temperature vs. output full-scale voltage output full-scale voltage v fs [v] ambient temperature ta [ c] 0 25 50 0 ? v = 0.20mv/ c ? v = 0.7mv/ c 0 standard measurement conditions and description ad dd =dv dd =5v v ref =2.0v r out =200 ? r ir =3.3k ? f clk =80mhz ta=25 c fig. 4 includes the temperature characteristics of external metal film resistor. input data in fig. 6=all 0 and 1 of rectangular wave; clock frequency=80mhz. example of representative characteristics
sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package outline unit : mm CXD2315Q 15
16 CXD2315Q sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.03 0.125 0.04 detail a : palladium a package outline unit : mm

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